/******************************************************************
 *  MRRM's write back unit                                        *
 *                                                                *
 *  This file is part of the MRRM project                         *
 *  <http://mrrm.googlecode.com/>                                 *
 *                                                                *
 *  Author(s):                                                    *
 *    -  Yuan Pengfei <coolypf@opencores.org>                     *
 *                                                                *
 ******************************************************************
 *                                                                *
 *  Copyright (C) 2010 AUTHORS                                    *
 *                                                                *
 *  This source file may be used and distributed without          *
 *  restriction provided that this copyright statement is not     *
 *  removed from the file and that any derivative work contains   *
 *  the original copyright notice and the associated disclaimer.  *
 *                                                                *
 *  MRRM is free software: you can redistribute it and/or modify  *
 *  it under the terms of the GNU General Public License as       *
 *  published by the Free Software Foundation, either version 3   *
 *  of the License, or (at your option) any later version.        *
 *                                                                *
 *  MRRM is distributed in the hope that it will be useful, but   *
 *  WITHOUT ANY WARRANTY; without even the implied warranty of    *
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the  *
 *  GNU General Public License for more details.                  *
 *                                                                *
 *  You should have received a copy of the GNU General Public     *
 *  License along with MRRM. If not, see                          *
 *  <http://www.gnu.org/licenses/>.                               *
 *                                                                *
 ******************************************************************/
 
`include "global.v"

module mrrm_test_wb;

parameter aw = `REGFILE_ADDR_WIDTH;
parameter mw = `MEMORY_ADDR_WIDTH;
parameter ow = `OPERAND_WIDTH;

// Interfaces
// Register file
wire [aw-1:0] addrx;
wire [aw-1:0] addry;
wire [ow-1:0] datax;
wire [ow-1:0] datay;
wire wrx;
wire wry;

// Write back
reg [2:1] W_itype;
reg [ow-1:0] W_valx;
reg [ow-1:0] W_valy;
reg [ow-1:0] W_valm;
reg [aw-1:0] W_dstx;
reg [aw-1:0] W_dsty;
reg W_wrx;
reg W_wry;


mrrm_wb temp_mrrm_wb(
	// RF interface
	.addrx(addrx), .addry(addry), .datax(datax), .datay(datay), .wrx(wrx), .wry(wry),
	// WB interface
	.W_itype(W_itype), .W_valx(W_valx), .W_valy(W_valy), .W_valm(W_valm),
	.W_dstx(W_dstx), .W_dsty(W_dsty), .W_wrx(W_wrx), .W_wry(W_wry)
	);

initial
begin
  W_itype = 2'b00;
  W_valx = 32'b00000000000000000000000000000000;
  W_valy = 32'b00000000000000000000000000000000;
  W_valm = 32'b00000000000000000000000000000000;
  W_dstx = 32'b00000000000000000000000000000000;
  W_dsty = 32'b00000000000000000000000000000000;
  W_wrx  = 0;
  W_wry  = 0;
  
  #50 W_wrx = 1;
  #50 W_wrx = 0;
  
  #50 W_wry = 1;
  #50 W_wrx = 0;
  
  #50 W_dstx = 32'b00000000000000000000000000000001;
  #50 W_dstx = 32'b00000000000000000000000000010001;
  #50 W_dstx = 32'b00000000000000000000001000010001;
  #50 W_dstx = 32'b00000000000000001000001000010001;
  #50 W_dstx = 32'b00000000001000001000001000010001;
  #50 W_dstx = 32'b00000010001000001000001000010001;
  #50 W_dstx = 32'b01000010001000001000001000010001;
  
  #50 W_dsty = 32'b00000000000000000000000000000001;
  #50 W_dsty = 32'b00000000000000000000000000010001;
  #50 W_dsty = 32'b00000000000000000000001000010001;
  #50 W_dsty = 32'b00000000000000001000001000010001;
  #50 W_dsty = 32'b00000000001000001000001000010001;
  #50 W_dsty = 32'b00000010001000001000001000010001;
  #50 W_dsty = 32'b01000010001000001000001000010001;
  
  #50 W_valy = 32'b00000000000000000000000000000001;
  #50 W_valy = 32'b00000000000000000000000000010001;
  #50 W_valy = 32'b00000000000000000000001000010001;
  #50 W_valy = 32'b00000000000000001000001000010001;
  #50 W_valy = 32'b00000000001000001000001000010001;
  #50 W_valy = 32'b00000010001000001000001000010001;
  #50 W_valy = 32'b01000010001000001000001000010001;
  
  #50 W_itype[2:1] = 2'b00;
  #50 W_valx = 32'b00000000000000000000000000000001;
  #0  W_valm = 32'b01000010001000001000001000010001;
  #50 W_valx = 32'b00000000000000000000000000010001;
  #0  W_valm = 32'b00000010001000001000001000010001;
  #50 W_valx = 32'b00000000000000000000001000010001;
  #0  W_valm = 32'b00000000001000001000001000010001;
  
  #50 W_itype[2:1] = 2'b01;
  #50 W_valx = 32'b00000000000000000000000000000001;
  #0  W_valm = 32'b01000010001000001000001000010001;
  #50 W_valx = 32'b00000000000000000000000000010001;
  #0  W_valm = 32'b00000010001000001000001000010001;
  #50 W_valx = 32'b00000000000000000000001000010001;
  #0  W_valm = 32'b00000000001000001000001000010001;
  
  #50 W_itype[2:1] = 2'b10;
  #50 W_valx = 32'b00000000000000000000000000000001;
  #0  W_valm = 32'b01000010001000001000001000010001;
  #50 W_valx = 32'b00000000000000000000000000010001;
  #0  W_valm = 32'b00000010001000001000001000010001;
  #50 W_valx = 32'b00000000000000000000001000010001;
  #0  W_valm = 32'b00000000001000001000001000010001;
  
  #50 W_itype[2:1] = 2'b11;
  #50 W_valx = 32'b00000000000000000000000000000001;
  #0  W_valm = 32'b01000010001000001000001000010001;
  #50 W_valx = 32'b00000000000000000000000000010001;
  #0  W_valm = 32'b00000010001000001000001000010001;
  #50 W_valx = 32'b00000000000000000000001000010001;
  #0  W_valm = 32'b00000000001000001000001000010001;
  
	#100 $stop;
end

initial
  begin
    $monitor("Time@%d, addrx=%h ,addry=%h ,datax=%h, datay=%h, wrx=%h, wry=%h",
      $time, addrx ,addry ,datax, datay, wrx, wry
    );
end

endmodule